This invention relates to physically non-distributed microprocessor based systems and, more particularly, the communication channel between functional components within a class of computer systems commonly known as personal computers.
A personal computer (PC) is comprised of several major functional components which may be basically defined as a microprocessor, a read/write memory (RAM), a mass storage device (e.g., hard drive or CD ROM), and an input/output (I/O) device (e.g., display, serial port, parallel ports, etc.). These functional components within the PC are interconnected by, and communicate via, a parallel data/address bus which is usually as wide as the processor data I/O path. The bus is typically of fixed physical length comprising a number of parallel copper traces on the PC's motherboard. In addition, there are provided a number of fixed tap points to the bus, e.g., edge connectors, din connectors, etc., to allow the customization of the PC's configuration by adding peripheral functions, memory, etc., or removing unused functionality.
While a bus provides a simple-minded mechanism for customization and communication within a PC, it has several limitations and unique problems associated with it. First, a bus is by nature, single transaction (e.g., only one functional unit can communicate with another at any given time and during this time, no other functional units can communicate with anything) and sequential (messages follow one after the other with considerable handshaking between functional units). A second problem of a bus is that all functional units connected to the bus must meet the electrical specifications and requirements of the bus even if these specifications and requirements are quite dated, technologically. Thirdly, because the bus is a generic interconnect in nature, it can not be truly optimized for communication between any specific subset of functional units without adversely affecting communication performance between another subset of functional units.
Fourth, the speed of the bus is substantially slower than might otherwise be obtainable. This is due to two primary issues: First, busses are composed of relatively long lengths of parallel traces in close proximity to one another and this results in high parasitic capacitive coupling between traces of the bus (i.e., electrical noise). This noise increases as the frequency, or speed, of the bus increases. Thus, noise margin requirements restrict the speed (and length) of the bus. The second issue relates to the unknown and highly variable electrical loading of the bus. The speed of the bus is inversely proportional to the capacitive load on the bus. This capacitive load is determined by the number of electrical connectors on the bus and the number of electrical connections to the bus. Since these numbers are variable, designers typically engineer the bus for worst case constraints. That is, the bus is typically slowed down to a rate that would sustain a worst case loading situation even though this may occur in one PC in a thousand.
Other major drawbacks of a bus are the need for electrical handshake signals and its fixed electrical data width (i.e., 8 bits, 16 bits, 32 bits, etc.) Handshake signals typically include READ, WRITE, MEM, I/O, WAIT/READY, etc. These signals are physical and are used to inform and control functional units (i.e., inform of the type of request, and control/synchronize between communicators.) Fixed data width limitations become problematic as chip data path widths exceed the width of the bus. As will be seen herein, defining handshaking and data size at the physical layer is less flexible than would be desired.
With the ever increasing demand for data manipulation in such applications as multimedia or graphics programs, the bottleneck of the bus becomes more acute. There have been many attempts to address and remedy this problem (e.g., VESA, Video local bus, PCI, etc.) but no solution offers greatly improved performance and complete scalability.
The present invention provides a system with the configuration flexibility of a bus-based PC while reducing the electrical problems. Commensurably, interfunctional-unit communication speed and flexibility are greatly enhanced. The present invention applies a point-to-point packetized interconnection structure to facilitate communication between functional units (e.g., processor, memory, disk, I/O, etc.) within a PC.
Because it is point-to-point, the interconnections scheme of the present invention is of relatively fixed electrical load and can, therefore, be optimized for speed. Furthermore, the packet protocol that will be more fully disclosed herein provides a means of eliminating the typical physical layer control signals of a bus and replacing them with link-layer control which is much more flexible.
In order to allow for interconnecting more than two functional units, the present invention may be expanded by any of several interconnect topologies, e.g., switches, rings, etc. Where speed and a high degree of parallel traffic is desired, a switch topology provides the best means, e.g., crossbar switch. If speed is important but parallel traffic patterns are not very common, a shuffle-type switch may make the most sense. In applications that are very cost sensitive, the present invention may also be expanded by means of a ring topology.
As will be made clear in the specific disclosure portion of this document, the packetized point-to-point interconnection scheme of the present invention improves speed and performance at reduced cost and with better noise characteristics (both internal electrical noise and radiated EMI) as compared to the bus interconnect currently employed within a PC.
Therefore, it is an object of the present invention to provide a new and improved PC, specifically, improving internal communication between microprocessor, memory, mass storage, I/O, etc. or any subset of these functional units. It is further an object of the invention to improve communication speed within a PC. It is further an object of the invention to reduce interconnection electrical noise within a PC. It is further and object of the invention to provide a more flexible interconnect means within a PC.
Accordingly, it is a general object of the present invention to provide a new and improved PC, specifically improving internal communication between microprocessor, memory, mass storage, I/O, etc. or any subset of these functional units.
It is a more specific object of the present invention to provide improved communication speed within a PC.
It is a still more specific object of the present invention to reduce interconnection electrical noise within a PC, and to provide a more flexible interconnect means.